this post was submitted on 10 Jun 2023
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RISC-V

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RISC-V (pronounced "risk-five") is a license-free, modular, extensible instruction set architecture (ISA).

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How a CPU works: Bare metal C on my RISC-V toy CPU (florian.noeding.com)
submitted 2 years ago by JRepin@lemmy.ml to c/riscv@lemmy.ml
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"I’ll walk through my steps of creating an emulator, compiling and linking C for bare metal, CPU design and finally the implementation of my toy RISC-V CPU."

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