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TSMC is working with equipment and material suppliers on the new method, multiple people with direct knowledge of the matter told Nikkei Asia, though commercialization could take several years.

To make the new method work, TSMC and its suppliers would have to devote a significant amount of time and effort to development as well as upgrade or replace numerous production tools and materials.

For B200 chipsets, for example, CoWoS makes it possible to combine two Blackwell graphic processing units and connect them with eight high bandwidth memories (HBMs), enabling fast data throughput and accelerated computing performance.

But as chip size grows to accommodate more transistors and to integrate more memory, the current industry standard -- 12-inch wafers with an area of approximately 70,685 sq.

Display and PCB makers are specialists when it comes to handling rectangular substrates, but chip production demands a higher level of equipment and material precision, industry executives and analysts said.

"This shift would require a significant overhaul of facilities, including upgrades to robotic arms, and automated material handling systems to process the different shapes of substrates," Li said.

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