RiscV

As you may have heard, Ubuntu 25.10 will only run on RISC-V devices with RVA23 profile extensions, a change made to allow the distro to take full advantage of newer hardware capabilities without backwards-looking compromise.

But if you’re worried that Ubuntu’s pivot to the RISC-V RVA23 profile would leave you without hardware to run it on (since, right now, no RVA23 devices are available) you can relax a little as a slate of RVA23-compatible chips are due to launch in 2026 – and some this year.

Given the lack of hardware on sale right now, some have questioned the move by Canonical. Yet, it didn’t happen in a vacuum. Its engineers have access to development hardware and close partnerships with silicon vendors. Not on sale doesn’t mean they don’t exist.

8 High-Performance RISC-V Cores UR-CP100 (up to 2.0GHz)

• 1 Cluster (4x UR-CP100 cores) sharing 4MB, total 8MB
• System-level cache: 16MB shared by 2 cluster (8 cores)

The Most Powerful RISC-V Core in Mass Production to Date - UR-CP100 (RV64GCBHX)

• 64-bit out-of-order 4-issue superscalar microarchitecture
• SPECCPU2006 single-core INT@10.4/GHz
• SPECCPU2006 single-core FP@12/GHz
• UltraRISC proprietary high-performance "X" instruction set extension

Compliant with RISC-V International Foundation Standards

• Fully Compliant with RVA22
• Compliant with RVA23* (excluding "V" extension)

Supports DDR4 Memory Stick, Up to 64GB

• Compatible with standard PC-grade memory stick (UDIMM)
• Supports standard DDR4 JEDEC JESD79-4A protocol
• Supports maximum speed of 3200MT/s
• Supports ECC

Supports UEFI Boot

• Supports ACPI, CPPC, SMBIOS
• Standardized boot support
• Native ISO file mounting
• More flexible boot options
• Enhanced security

Supports Commodity NVMe SSDs (PCIe Gen4 4-lane)

Supports High-Speed USB3 5Gbps

Onboard Full-Size PCIe Connector with PCIe Gen4 16-lane

• https://bugs.launchpad.net/ubuntu/+source/ubuntu-release-upgrader/+bug/2111715
• https://www.omgubuntu.co.uk/2025/06/ubuntu-riscv-rva23-support
• https://9to5linux.com/canonical-plans-for-a-fully-functional-desktop-session-on-risc-v-with-ubuntu-25-10

cross-posted from: https://lemmy.world/post/32690684

Ever wondered how the brain of your computer works? This guide will take you from knowing nothing about processor design to having Tiny Vedas, a complete, open-source RISC-V processor running on your machine.

In this course, we'll design and implement a RISC-V processor. It's going to be a small processor, but it will allow us to see 90% of computer architecture concepts.

Important disclaimer: This course is not meant to be a comprehensive guide to RISC-V or processor design. It's intended to give you a quick and fast track to building a RISC-V processor from the ground up.

No prerequisites required - this course is targeted to people straight out of high school.

cross-posted from: https://rss.ponder.cat/post/204150

Intel, CPUs, and the concept of "badness" aren't necessarily things you'd want to shout about, what with numerous well-documented issues afflicting Intel's recent processors. But a new Oregon-based startup called AheadComputing is leaning hard on the Intel provenance of its founders while claiming that it is creating, "the biggest, baddest CPU in the world." And it's going to do it via IPC or instructions per clock, not cranking up the operating frequencies or throwing in more cores.

That is some statement. All four of AheadComputing's founders had long careers at Intel, dating all the way back to ye olde 386 processor through to the latest Intel Core-branded chips. What's more, AheadComputing also appointed CPU design legend Jim Keller to its board in March. That's at least a vote of confidence, even if it seems unlikely Keller will be involved in the design of AheadComputing's CPUs.

The company is very young, having launched in July last year with a plan to, "develop and license breakthrough, high-performance 64-bit RISC-V processor cores." RISC-V, of course, is an open-source instruction set that exists to present a more modern and cost effective alternative to the proprietary x86 and Arm standards.

Currently, RISC-V chips tend to be found in embedded applications and commercial devices. RISC-V has yet to make much of an impact in PCs or phones, for instance.

Exactly how AheadComputing is going to deliver on that promise of the "biggest, baddest CPU in the world" isn't totally clear beyond the focus in IPC. It's a fabless startup, which means it won't manufacture chips itself. But then the likes of AMD and Nvidia are fabless, too. It's really only Intel that designs and manufactures its own chips, and that business is coming under increasing pressure.

Apple's M4 currently has significantly better IPC than any Intel or AMD CPU. (Image credit: Apple)

According to AheadComputing's CEO Debbie Marr, "the x86 ecosystem is fiercely defending its territory but is destined to lose in the end." As for Arm, she says, "we anticipate that the ARM ecosystem will experience considerable strain in the coming years. If ARM's current customers are pressured excessively, they will consider transitioning to an alternative architecture like RISC-V."

In response, AheadComputing claims it will, "demonstrate leadership in CPU performance and performance per watt in a very short timeframe and start building the second generation of products that will demonstrate our commitment to a roadmap with large gains in performance generation over generation."

AheadComputing says it will achieve that via IPC, or instructions processed per clock, as opposed to operating frequency or adding cores. "If the performance and efficiency from the multi-core scaling era are slowing down, then it's time for the CPU designers to find a different way to use the additional gates from new process technologies. CPU designers must look towards IPC. This will require increasing the functions for each core rather than increasing the number of cores. If we do this intelligently, AheadComputing will provide performance improvements regardless of workload parallelism," says co-founder Jonathan Pearce.

That latter point could be critical. When Intel's plans for 10 GHz-plus computing hit the wall towards the latter end of the 2000's, the company dramatically changed tack in favour of multi-core computing as a way to add performance in the absence of substantial clockspeed improvements.

Adding lots of cores isn't always the best way to improve performance. (Image credit: Intel)

The problem with adding cores is that it relies on multi-threaded workloads. That's fine for many tasks, like 3D rendering. But it's not a magic bullet for every computational task. Indeed, that's why AMD's eight-core Ryzen 7 9800X3D is the weapon of choice for PC gaming, currently. Adding another eight cores in the form of the Ryzen 9 9950X3D typically doesn't do a whole lot for gaming performance.

Whatever, aside from that focus on IPC as opposed to adding cores, AheadComputing isn't going into any detail. For sure, it will be years before the company's CPU core designs have any chance of showing up in a device you can actually buy.

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But the focus on IPC is still interesting. Right now, Apple's M Series CPUs offer the best IPC in a consumer chip by absolutely miles. The latest M4 easily outperforms anything from Intel or AMD when it comes to a single software thread, despite running at significantly lower clockspeeds. Metrics vary, but the M4 probably has a lead of at least 30% in terms of pure IPC versus the best AMD and Intel CPUs, and quite possibly more.

Personally, if you offered me a CPU with either 50% more IPC or 50% more cores, I'd take the IPC every time. That will deliver in almost any circumstance, while multi-core CPUs can be a bit more hit and miss. Aiming for improved IPC also tends to make for better efficiency, which is great for mobile PCs.

Anywho, for now we'll have to chalk AheadComputing down as a slow burn. The company has strong provenance, but it's anyone's guess as to whether it will, in reality, make an impact. My best guess is that if it manages to come up with an interesting core design, it'll get snapped up by one of the big boys, just as the startup Nuvia was bought by Qualcomm and its Oryon CPU cores ended up in the new Snapdragon X chips.

And all of that is before you even begin to ponder the odds of any RiSC-V chip making an impact on the PC. Industry watchers have been predicting Arm chips would take over the PC for decades. That still hasn't happened.

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Open-source RISC-V cores are increasingly demanded in domains like automotive and space, where achieving high instructions per cycle (IPC) through superscalar and out-of-order (OoO) execution is crucial. However, high-performance open-source RISC-V cores face adoption challenges: some (e.g. BOOM, Xiangshan) are developed in Chisel with limited support from industrial electronic design automation (EDA) tools. Others, like the XuanTie C910 core, use proprietary interfaces and protocols, including non-standard AXI protocol extensions, interrupts, and debug support.

In this work, we present a modified version of the OoO C910 core to achieve full RISC-V standard compliance in its debug, interrupt, and memory interfaces. We also introduce CVA6S+, an enhanced version of the dual-issue, industry-supported open-source CVA6 core. CVA6S+ achieves 34.4% performance improvement over CVA6 core.

We conduct a detailed performance, area, power, and energy analysis on the superscalar out-of-order C910, superscalar in-order CVA6S+ and vanilla, single-issue in-order CVA6, all implemented in a 22nm technology and integrated into Cheshire, an open-source modular SoC. We examine the performance and efficiency of different microarchitectures using the same ISA, SoC, and implementation with identical technology, tools, and methodologies. The area and performance rankings of CVA6, CVA6S+, and C910 follow expected trends: compared to the scalar CVA6, CVA6S+ shows an area increase of 6% and an IPC improvement of 34.4%, while C910 exhibits a 75% increase in area and a 119.5% improvement in IPC. However, efficiency analysis reveals that CVA6S+ leads in area efficiency (GOPS/mm2), while the C910 is highly competitive in energy efficiency (GOPS/W). This challenges the common belief that high performance in superscalar and out-of-order cores inherently comes at a significant cost in area and energy efficiency.

The KDE Frameworks are a set of 83 add-on libraries for programming with Qt. Part of it is also the syntax highlighting engine, used not only by KDE applications like Kate and KDevelop; but also by some others like Qt Creator.

Version 6.14 of KDE Framworks add support for RISC-V instructions/registers/… in GNU Assembler. Including some vendor-specific instructions.